|Keynote Speaker 1||Dipl. Ing. Paul Blinzer, Fellow System SW, AMD Inc., USA|
|About the Speaker||Mr. Paul Blinzer is a Fellow at AMD in the Platform Software Group, has contributed on a wide range of technologies over his 24 years at AMD and holds over 40 issued patents. His most recent area of work leverages the capabilities of advanced data fabrics, accelerators and CPUs into application and operating system programming models. He is participating in workgroups of several standards organizations and was serving as the Chairperson of the System Architecture Workgroup of the HSA Foundation. Mr. Blinzer lives in the Seattle/WA area, enjoys working on the forefront of technology and many outdoor activities, in accordance to the assumptions about the general lifestyle in the Pacific Northwest of the United States.|
|Keynote Topic||“The Flexibility Conundrum – Custom Accelerators vs Common Software“|
|Abstract||With ever more demand for compute performance and large dataset processing for machine learning, high performance compute and other domains, efficiently integrating sophisticated, custom accelerators into established large application frameworks that initially were focusing on host CPU processing becomes ever more challenging. The presentation outlines existing challenges and outlines ongoing work in the AMD Research and Advanced Development work on explorations to simplify integration of scalable custom domain accelerator functionality into well-established, low overhead application programming models.|
|Keynote Speaker 2||Prof. Dr. Akash Kumar, TU Dresden|
|About the Speaker||Akash Kumar is a chaired Professor of Processor Design (with tenure) in the department of Computer Science at Technische Universität Dresden (TUD), Germany. From 2009 to 2015, he was with the Department of Electrical and Computer Engineering, National University of Singapore (NUS). He received the joint Ph.D. degree in electrical engineering in embedded systems from Eindhoven University of Technology (TU/e) and National University of Singapore (NUS), in 2009; joint Master’s degree from TU/e and NUS in 2005 in embedded systems and Bachelor of Computer Engineering degree from NUS in 2002.|
His research interests span various aspects of design automation, especially reconfigurable architectures. He has published close to 250 articles in premier international conferences and journals in the area of design automation, including 4 monographs and 6 book chapters. Together with his research group, he has released many open-source tool flows for system design and analysis to allow the community to reproduce their results and to further research in the related areas.
He serves (or has recently served) on the program committee of renowned conferences in the area like DAC, DATE, FPL and CASES. He was the program chair of International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES’18 and ’19) and program chair for IEEE International Conference on Field Programmable Logic and Applications 2021.
|Keynote Topic||Reinventing Reconfigurability|
|Abstract||Most of the FPGA designs are based on Look-up Tables. LUTs provide programmability by storing the results of a pre-computed output function. Changing or reconfiguring a LUT for another output function is trivial, since one has to only reprogram the memory contents of an LUT. While extremely easy to reconfigure, it does come at a high cost in terms of area. What if we could offer reconfigurability at an even smaller level? In this keynote, I will talk about reconfigurable transistors, which can be programmed to operate as an NMOS or a PMOS transistor at run-time. This not only has the potential to provide reconfigurable circuits with less area, but also provide security against side-channel and reverse engineering attacks.|