Full Paper Presentations	30 mins (20 min Presentation + 10 mins Q/A)
Poster Presentations	5 mins Pitch Presentation

Day 1: September 27, 2023

08:45am – 09:00am: Conference Opening (Chaired by Prof. Dr.-Ing. Marc Reichenbach) 09:00am – 10:00am: Keynote 1 – Dipl. Ing. Paul Blinzer, AMD, Inc. (Chaired by Prof. Dr.-Ing. Marc Reichenbach) 10:00am – 10:30am: Coffee Break 10:30am – 12:30pm: Session 1 – Neural Networks (4 papers) 12:30pm – 02:00pm: Lunch 02:00pm – 03:00pm: Keynote 2 – Prof. Dr. Akash Kumar, TU Dresden (Chaired by Prof. Dr.-Ing. Diana Göhringer) 03:00pm – 03:30pm: Coffee Break 03:30pm – 05:00pm: Session 2 – Design Methods and Tools (3 papers)

Session 1: Neural Networks I

• Accelerating Graph Neural Networks in Pytorch With HLS and Deep Dataflows Jose Nunez-Yanez • A convolution neural network based displaced vertex trigger for the Belle II experiment Kai Unger, Jürgen Becker, Christian Kiesling, Yichuan Ma, Marc Neu, Elia Schmidt, Ulrike Zweigart, Felix Meggendorfer • On-FPGA Spiking Neural Networks for Multi-Variable End-to-End Neural Decoding Gianluca Leone, Luca Martis, Luigi Raffo, Paolo Meloni • Implementation of a perception system for autonomous vehicles using a~detection-segmentation network in SoC FPGA Maciej Baczmanski, Mateusz Wasala, Tomasz Kryjak

Session 2: Design Methods and Tools

• High-Level Synthesis of Memory Systems for Decoupled Data Orchestration Usui Masayuki, Shinya Takamaeda-Yamazaki • Rapid Prototyping of Complex Micro-architectures through High-Level Synthesis Sara Sadat Hoseininasab, Caroline Collange, Steven Derrien • Design Space Exploration of Application Specific Number Formats targeting an FPGA Implementation of SPICE Jonas Gehrunger, Christian Hochberger

Day 2: September 28, 2023

08:30am – 9:45am: Session 3 – Special Session on Near and in-Memory Computing (3 papers) 09:45am – 10:00am: Coffee Break 10:00am – 11:30pm: Session 4 – Security and Fault Tolerance (3 papers) 11:30pm – 12:45pm: Lunch 12:45pm – 02:15pm: Session 5 – Neural Networks II (3 papers) 02:15pm – 02:30pm: Coffee Break 02:30pm – 04:00pm: Session 6 – Applications and Architectures (3 papers) 04:00pm – Open End: Tagebau Cottbus-Nord Local Tour + Dinner at Lindner Hotel (Dinner starts at 7:30pm)

Session 3: Special Session on Near and in-Memory Computing (Session Chair: Marc Reichenbach)

• TAPRE-HBM: Trace-Based Processor Rapid Emulation using HBM on FPGAs Johannes Knödtel , Hector Gerardo, Muñoz Hernandez, Alexander Lehnert, Gia Bao Thieu, Sven Gesper, Guillermo Payá-Vayá, Marc Reichenbach • An Almost Fully RRAM-based LUT Design for Reconfigurable Circuits Philipp Grothe, Saleh Mulhem, Mladen Berekovic • A Light-weight Vision Transformer toward Near-Memory Computation on an FPGA Takeshi Senoo, Ryota Kayanoma, Akira Jinguji, Hiroki Nakahara

Session 4: Security and Fault Tolerance (Session Chair: Thilo Pionteck)

• DNN Model Theft through Trojan Side Channel on Edge FPGA Accelerator Srivatsan Chandrasekar, Siew Kei Lam, Srikanthan Thambipillai • Towards Secure and Efficient Multi-generation Cellular Communications: Multi-mode SNOW-3G/V ASIC and FPGA Implementations Evangelia Konstantopoulou, George Athanasiou, Nicolas Sklavos • Increasing the Fault Tolerance of COTS FPGAs in Space: SEU Mitigation Techniques on MPSoC George Pagonis, Vasileios Leon, Dimitros Soudris, George Lentaris

Session 5: Neural Networks II (Session Chair: Hiroki Nakahara)

• Evolutionary FPGA-based Spiking Neural Networks for Continual Learning Andrés Otero, Guillermo Sanillorente, Eduardo de la Torre, José Nunez-Yanez • More Efficient CMMs on FPGAs: Instantiated Ternary Adders for Computation Coding Alexander Lehnert, Hans Rosenberger, Ralf Müller, Marc Reichenbach • Energy Efficient DNN Compaction for Edge Deployment Bijin Baby, Dipika Deb, Benuraj Sharma, Kirthika Vijayakumar, Satyajit Das

Session 6: Applications and Architectures (Session Chair: Shinya Takamaeda-Yamazaki)

• FPGA-Integrated Bag of Little Bootstraps Accelerator for Approximate Database Query Processing Vitalii Burtsev, Martin Wilhelm, Anna Drewes, Balasubramanian Gurumurthy, David Broneske, Thilo Pionteck, Gunter Saake • Scalable and Energy-Efficient NN acceleration with GPU-ReRAM architecture Rafal Fão de Moura, Luigi Carro • On Guaranteeing Schedulability of Periodic Real-time Hardware Tasks under ReconOS64 Lennart Clausing, Zakarya Guettatfi, Paul Kaufmann, Christian Lienen, Marco Platzner

Day 3: September 29, 2023

09:00am – 11:00am: Session 7 – Frameworks, Emulators, and APIs (4 papers) 11:00am – 11:20am: PhD Forum Presentations (4 papers, 5 min Presentations) 11:20am – 12.10pm: Poster Session Discussion + Coffee Break 12:10pm – 12:20pm: Conference Closing and Best Paper Award 12:20pm – 01:30pm: Lunch

Session 7: Frameworks, Emulators, and APIs (Session Chair: Luigi Carro)

• On the OpenCL Support for Streaming Fixed-Function Accelerators on Embedded SoC FPGAs Panagiotis Mousouliotis, Topi Leppanen, Pekka Jaaskelainen, Nikos Petrellis, Panagiotis Christakos, Georgios Keramidas, Christos Antonopoulos, Nikolaos Voros • ArcvaVX: OpenVX Framework for Adaptive Reconfigurable Computer Vision Architectures Lester Kalms, Matthias Nickel, Diana Goehringer • NVMulator: A Configurable Open-Source Non-Volatile Memory Emulator for FPGAs Sajjad Tamimi, Arthur Bernhardt, Florain Stock Illia Petrov, Andreas Koch • Memory-Aware Scheduling for a Resource-Elastic FPGA Operating System Shaden Alismail, Dirk Koch

Session Phd Forum Presentations: (Session Chair: Guillermo Payá Vayá)

• Radiation Tolerant Reconfigurable Hardware Architecture Design Methodology Eike Trumann, Gia Bao Thieu, Johannes Schmechel, Kirsten Weide-Zaage, Katharina Schmidt, Dorian Hagenah, Guillermo Payá Vayá • A Control Data Acquisition System Architecture for MPSoC-FPGAs in Computed Tomography Daniele Passaretti, Thilo Pionteck • Simulation and Modelling for Network-on-Chip based MPSoC Julian Haase, Diana Goehringer • A Design-Space Exploration Framework for Application-Specification Machine Learning targeting Reconfigurable Computing Safdar Mahmood, Michael Hübner, Marc Reichenbach

END OF THE CONFERENCE